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Proceedings Paper

Noble approaches on double-patterning process toward sub-15nm
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Paper Abstract

Double Patterning process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device[1], and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pitch-Quadrupling (SAQP) achieved 11nm hp as introduced in previous our study[2]. Sa-MP has been required to mitigate a process complexity and cost impact. Furthermore, Process variability, Pattern fidelity, CD metrology for sub 20nm pattern also has to be considered. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened.

Paper Details

Date Published: 29 March 2013
PDF: 9 pages
Proc. SPIE 8685, Advanced Etch Technology for Nanopatterning II, 86850M (29 March 2013); doi: 10.1117/12.2011962
Show Author Affiliations
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)
Kenichi Oyama, Tokyo Electron AT Ltd. (Japan)
Arisa Hara, Tokyo Electron AT Ltd. (Japan)
Sakurako Natori, Tokyo Electron AT Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron AT Ltd. (Japan)
Masatoshi Yamato, Tokyo Electron AT Ltd. (Japan)

Published in SPIE Proceedings Vol. 8685:
Advanced Etch Technology for Nanopatterning II
Ying Zhang; Gottlieb S. Oehrlein; Qinghuang Lin, Editor(s)

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