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Proceedings Paper

Controlled replication: reduce the capacity occupied by redundant replicas in tiled chip multiprocessors
Author(s): Hao Li; Lunguo Xie
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Paper Abstract

The design of cache system for Chip Multiprocessor (CMP) face many challenges because future CMPs will have more cores and greater on-chip cache capacity. There are two base design schemes about L2 cache: private scheme in which each L2 slice is treated as a private L2 cache and shared scheme in which all L2 slices are treated as a large L2 cache shared by all cores. Private caches provide the lowest hit latency but reduce the total effective cache capacity. A shared L2 cache increases the effective cache capacity but has long hit latencies when data is on a remote tile. This paper present a new Controlled Replication (CR) policy to reduce the capacities occupied by redundant shared replicas. the new CR policy increases the effective capacity than victim replication scheme and has lower hit latency than shared scheme. We evaluate the various schemes using full-system simulation of parallel applications. Results show that CR reduces the average memory access latency of shared scheme by an average of 13%, providing better overall performance than victim replication and shared schemes.

Paper Details

Date Published: 4 March 2013
PDF: 8 pages
Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 87684W (4 March 2013); doi: 10.1117/12.2011858
Show Author Affiliations
Hao Li, National Univ. of Defense Technology (China)
Lunguo Xie, National Univ. of Defense Technology (China)


Published in SPIE Proceedings Vol. 8768:
International Conference on Graphic and Image Processing (ICGIP 2012)
Zeng Zhu, Editor(s)

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