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Proceedings Paper

Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning
Author(s): Gerard Luk-Pat; Ben Painter; Alex Miloslavsky; Peter De Bisschop; Adam Beacham; Kevin Lucas
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Paper Abstract

For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.

Paper Details

Date Published: 12 April 2013
PDF: 12 pages
Proc. SPIE 8683, Optical Microlithography XXVI, 868312 (12 April 2013); doi: 10.1117/12.2011539
Show Author Affiliations
Gerard Luk-Pat, Synopsys, Inc. (United States)
Ben Painter, Synopsys, Inc. (United States)
Alex Miloslavsky, Synopsys, Inc. (United States)
Peter De Bisschop, IMEC (Belgium)
Adam Beacham, Synopsys, Inc. (Canada)
Kevin Lucas, Synopsys, Inc. (United States)


Published in SPIE Proceedings Vol. 8683:
Optical Microlithography XXVI
Will Conley, Editor(s)

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