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Proceedings Paper

Diffraction pattern based optimization of lithographic targets for improved printability
Author(s): Shayak Banerjee; Kanak B. Agarwal
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Paper Abstract

Conventional resolution enhancement techniques (RET) are becoming increasingly inadequate at addressing the challenges of sub-wavelength lithography. In particular, features show high sensitivity to process variation in low-k1 lithography. While advanced mask optimization techniques such as process window optical proximity correction (PWOPC) exist to address this, they modify electrical properties of shapes in a way that is incommunicable to the designer. A more design-aware approach for improving printability is to perform retargeting, which is a modification of target layout shapes to improve their process window. Retargeting can be performed rule-based or model-based. The former has fast runtime but is not a scalable technique since rules cannot cover the entire search space of two-dimensional shape configurations, especially with technology scaling. The latter provides more coverage of complex 2-D optical interactions compared to rules, but suffers from high runtime and inability to communicate modified design intent back to the designer. In this paper, we explore an alternative approach to retargeting which overcomes the drawbacks of both these methods. We develop a target optimization method based on knowledge of source and the diffraction pattern of the layout. We demonstrate that target optimization can be performed at fast runtime using just the Fourier transform of the layout. This approach is more scalable than rule-based retargeting, but also allows communication of modified design intent by integration into extraction tools.

Paper Details

Date Published: 29 March 2013
PDF: 11 pages
Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 868405 (29 March 2013); doi: 10.1117/12.2011532
Show Author Affiliations
Shayak Banerjee, IBM Corp. (United States)
Kanak B. Agarwal, IBM Corp. (United States)


Published in SPIE Proceedings Vol. 8684:
Design for Manufacturability through Design-Process Integration VII
Mark E. Mason; John L. Sturtevant, Editor(s)

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