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Proceedings Paper

Capability study and challenges to sub-2x nm node contact hole patterning
Author(s): Wan-Lin Kuo; Ya-Ting Chan; Meng-Feng Tsai; Yi-Shiang Chang; Chia-Chi Lin; Ming-Chien Chiu; Chun-Hsun Chen; Hung-Ming Wu; Mao-Hsing Chiu
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Paper Abstract

As the scaling down of design rule for high density memory device continues, the contact hole size shrinkage becomes one of the major challenges to patterning. Many shrinkage approaches have been introduced after litho. process, such as chemical shrink, PR reflow, RIE shrink, etc. However, CD uniformity control for these shrink processes is critical, and minimum pitch size is still dominated by the resolution limitation of lithography tools. In this paper, we adopt SADP (self-aligned double patterning) process combined with additional non-critical mask step to form 32nm hp elliptical single row dense and isolated contact holes. The CD uniformity is well controlled by SADP process, and chip size reduction is achievable by this high-density single row layout compared with interlace contact hole design. We also compared this new approach with chemical shrink process, and both the CD uniformity and resolution limit are improved. With optimized step-by-step etch process, we have successfully demonstrated the contact hole patterns on full-structure substrate. For the future application toward sub-2x nm node, this approach is also expectable with mature SADP process.

Paper Details

Date Published: 29 March 2013
PDF: 7 pages
Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 86821G (29 March 2013); doi: 10.1117/12.2011434
Show Author Affiliations
Wan-Lin Kuo, Powerchip Semiconductor Corp. (Taiwan)
Ya-Ting Chan, Powerchip Semiconductor Corp. (Taiwan)
Meng-Feng Tsai, Powerchip Semiconductor Corp. (Taiwan)
Yi-Shiang Chang, Powerchip Semiconductor Corp. (Taiwan)
Chia-Chi Lin, Powerchip Semiconductor Corp. (Taiwan)
Ming-Chien Chiu, Powerchip Semiconductor Corp. (Taiwan)
Chun-Hsun Chen, Powerchip Semiconductor Corp. (Taiwan)
Hung-Ming Wu, Powerchip Semiconductor Corp. (Taiwan)
Mao-Hsing Chiu, Powerchip Semiconductor Corp. (Taiwan)


Published in SPIE Proceedings Vol. 8682:
Advances in Resist Materials and Processing Technology XXX
Mark H. Somervell, Editor(s)

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