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Proceedings Paper

Sub-22 nm silicon template nanofabrication by advanced spacer patterning technique for NIL applications
Author(s): Jong-Moon Park; Kun-Sik Park; Dong-Pyo Kim; Seong-Ook Yoo; Jin-Ho Lee
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Paper Abstract

A spacer patterning technique using a poly-Si micro-feature and a SiO2 spacer has been demonstrated to achieve sub-22 nm structures with conventional semiconductor equipments. The sub-22 nm structures have been fabricated by a plasma etching of Si substrate with a spacer oxide mask of which dimension is accurately controlled by the deposited film thickness. The profile of the Si nano-feature was influenced by an O2 flow rate during Si etching in inductively coupled plasma (ICP). As the O2 flow rate was decreased, the etch profile was improved vertically even though the etch rate of Si was slightly decreased. We obtained a 6-inch Si template with both nano- and micro-features of positive shape used for a master mold in nanoimprint lithography (NIL). The nano-sized Si features showed 22-nm width and 145-nm height with the slope of 87°. Further size reduction by anisotropic wet etching with KOH solution was also investigated.

Paper Details

Date Published: 26 March 2013
PDF: 8 pages
Proc. SPIE 8680, Alternative Lithographic Technologies V, 86802B (26 March 2013); doi: 10.1117/12.2011400
Show Author Affiliations
Jong-Moon Park, Electronics and Telecommunications Research Institute (Korea, Republic of)
Kun-Sik Park, Electronics and Telecommunications Research Institute (Korea, Republic of)
Dong-Pyo Kim, Electronics and Telecommunications Research Institute (Korea, Republic of)
Seong-Ook Yoo, Electronics and Telecommunications Research Institute (Korea, Republic of)
Jin-Ho Lee, Electronics and Telecommunications Research Institute (Korea, Republic of)


Published in SPIE Proceedings Vol. 8680:
Alternative Lithographic Technologies V
William M. Tong, Editor(s)

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