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Proceedings Paper

Process variability of self-aligned multiple patterning
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Paper Abstract

EUV lithography is one of the most promising techniques for sub 20nm half pitch HVM devices, however it is well known that EUV lithography solutions still face significant challenges. Therefore we have focused on 193 based self-aligned multiple patterning, because SAMP(SADP to SAQP) easily enables fine periodical patterning. As you know, these spacer based techniques have already been applied to NAND,DRAM,Logic mass productions. We have already introduced innovative resist core based SADP/SAQP techniques and have demonstrated results in past SPIE sessions.[1][2][3][4] Although SAMP technique can be easily extend to the gridded pattern for 1D layout, the resolution limit of gridded design rule will strongly depend on hole pitch shrink technique for the cut-pattern. In this paper, we will introduce GDR demonstration result of the 10nm logic node, and discuss about the process variability relevant to them.

Paper Details

Date Published: 29 March 2013
PDF: 6 pages
Proc. SPIE 8682, Advances in Resist Materials and Processing Technology XXX, 86820C (29 March 2013); doi: 10.1117/12.2011385
Show Author Affiliations
Kenichi Oyama, Tokyo Electron Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron Ltd. (Japan)
Arisa Hara, Tokyo Electron Ltd. (Japan)
Sakurako Natori, Tokyo Electron Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)

Published in SPIE Proceedings Vol. 8682:
Advances in Resist Materials and Processing Technology XXX
Mark H. Somervell, Editor(s)

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