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Proceedings Paper

Manufacturability of computation lithography mask: current limit and requirements for sub-20nm node
Author(s): Jin Choi; In-Yong Kang; Ji Soong Park; In Kyun Shin; Chan-Uk Jeon
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Paper Abstract

The computational lithography such as inverse lithography technique (ILT) or source mask optimization (SMO) is considered as the necessary technique for the extremely low k1 lithography process of sub-20nm node. The ideal curvilinear mask design for computational lithography gives the impacts and requires many changes on the photomask fabrication from mask data preparation to measurement and inspection. In this paper, we present the current status and new requirements for the computational lithography mask in viewpoint of the manufacturability for mass production. The manufacturability of computational lithography mask can be realized by the predictable and manageable patterning quality. Here, we have proposed new data flow for ILT which covers what the preferred target design is for ILT, new verification method, required mask model accuracy, and resolution improvement method. Furthermore, considering acceptable writing time (<24 hours) and computation limit on convolution, the current ILT technique is shown to have the limit of application area.

Paper Details

Date Published: 12 April 2013
PDF: 9 pages
Proc. SPIE 8683, Optical Microlithography XXVI, 86830L (12 April 2013); doi: 10.1117/12.2011341
Show Author Affiliations
Jin Choi, Samsung Electronics Co., Ltd. (Korea, Republic of)
In-Yong Kang, Samsung Electronics Co., Ltd. (Korea, Republic of)
Ji Soong Park, Samsung Electronics Co., Ltd. (Korea, Republic of)
In Kyun Shin, Samsung Electronics Co., Ltd. (Korea, Republic of)
Chan-Uk Jeon, Samsung Electronics Co., Ltd. (Korea, Republic of)


Published in SPIE Proceedings Vol. 8683:
Optical Microlithography XXVI
Will Conley, Editor(s)

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