Share Email Print
cover

Proceedings Paper

Toward 7nm target on product overlay for C028 FDSOI technology
Author(s): Maxime Gatefait; Bertrand Le-Gratiet; Pierre Jerome Goirand; Auguste Lam; Richard Van Haren; Anne Pastol; Maya Doytcheva; Xing Lan Liu; Jan Beltman
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

The continuous need for lithography overlay performance improvement is a key point for advanced integrated circuit manufacturing. Overlay control is more and more challenging in the 2x nm process nodes regarding functionality margin of the chip and tool capability. Transistor architecture rules which are set, confirm poly to contact space as the most critical one for 28nm technology node. Critical Dimension variability of these layers, even with best in class process stability, in addition to design constraint lead to on product overlay specifications of around 7nm. In order to ensure that the target is met in production environment and to identify potential ways for improvement, identification of the contributors to overlay errors is essential. We have introduced a novel budget breakdown methodology using both bottom-up and top-down overlay data. For the bottom up part, we have performed extensive testing with very high sampling scheme so as to quantify the main effects. In-line overlay metrology data has been used for top down approach to verify the overall performance in production. In this paper we focused on the 28nm contact to gate overlay in a FDSOI process. The initial inconsistency between bottom up and top down results led us to further exploration of the root cause of these inconsistencies. We have been able to highlight key figures to focus on, like reticle heating, wafer table contamination and etch processing effects. Finally, we conclude on 7nm overlay target achievement feasibility in high volume manufacturing environment.

Paper Details

Date Published: 10 April 2013
PDF: 8 pages
Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 868105 (10 April 2013); doi: 10.1117/12.2011099
Show Author Affiliations
Maxime Gatefait, STMicroelectronics (France)
Bertrand Le-Gratiet, STMicroelectronics (France)
Pierre Jerome Goirand, STMicroelectronics (France)
Auguste Lam, STMicroelectronics (France)
Richard Van Haren, ASML Netherlands B.V. (Netherlands)
Anne Pastol, ASML Netherlands B.V. (Netherlands)
Maya Doytcheva, ASML Netherlands B.V. (Netherlands)
Xing Lan Liu, ASML Netherlands B.V. (Netherlands)
Jan Beltman, ASML Netherlands B.V. (Netherlands)


Published in SPIE Proceedings Vol. 8681:
Metrology, Inspection, and Process Control for Microlithography XXVII
Alexander Starikov; Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top