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Proceedings Paper

Reflective electron beam lithography: lithography results using CMOS controlled digital pattern generator chip
Author(s): Thomas Gubiotti; Jeff Fuge Sun; Regina Freed; Francoise Kidwingira; Jason Yang; Chris Bevis; Allen Carroll; Alan Brodie; William M. Tong; Shy-Jay Lin; Wen-Chuan Wang; Luc Haspeslagh; Bart Vereecke
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Paper Abstract

Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed. Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be presented.

Paper Details

Date Published: 26 March 2013
PDF: 11 pages
Proc. SPIE 8680, Alternative Lithographic Technologies V, 86800H (26 March 2013); doi: 10.1117/12.2010722
Show Author Affiliations
Thomas Gubiotti, KLA-Tencor Corp. (United States)
Jeff Fuge Sun, KLA-Tencor Corp. (United States)
Regina Freed, KLA-Tencor Corp. (United States)
Francoise Kidwingira, KLA-Tencor Corp. (United States)
Jason Yang, KLA-Tencor Corp. (United States)
Chris Bevis, KLA-Tencor Corp. (United States)
Allen Carroll, KLA-Tencor Corp. (United States)
Alan Brodie, KLA-Tencor Corp. (United States)
William M. Tong, KLA-Tencor Corp. (United States)
Shy-Jay Lin, Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan)
Wen-Chuan Wang, Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan)
Luc Haspeslagh, IMEC (Belgium)
Bart Vereecke, IMEC (Belgium)

Published in SPIE Proceedings Vol. 8680:
Alternative Lithographic Technologies V
William M. Tong, Editor(s)

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