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Proceedings Paper

Flare management for 40-nm logic devices
Author(s): Yuusuke Tanaka; Takao Tamura; Masashi Fujimoto; Kyoichi Tsubata; Naka Onoda; Kiyoshi Fujii
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Paper Abstract

Since flare-related CD variation was observed in some 40-nm test chips, we evaluated the flare level of an ArF immersion scanner by the Kirk method. We found that the tool flare for a 1.3-μm pad was more than 5% and the short-range flare (scattering range < 10 μm) was quite large when the optics were degraded. Optics maintenance reduced the tool flare to about 2%. An evaluation of the impact of short-range flare on the space CDs of 40-nm logic devices revealed it to be quite large. The point spread function for flare was determined from measured flare data, and the flare density was calculated for various patterns. A simulation analysis showed that the measured CD error was closely related to flare density. Since the impact of a change in dose on space CD is nonlinear, the impact of a change in flare is also nonlinear. Simulations using tool flare and flare density can predict most of the CD error. In the active layer of 40-nm logic devices, the flare density is generally in the range of 40-70% for critical space patterns. Varying the dose control pattern from small-area L/S (< 5 μm square) to large-area L/S (50 μm square) should reduce the impact of flare on space CD. Patterns with a medium flare density are preferable for dose control.

Paper Details

Date Published: 12 April 2013
PDF: 8 pages
Proc. SPIE 8683, Optical Microlithography XXVI, 86832E (12 April 2013); doi: 10.1117/12.2010082
Show Author Affiliations
Yuusuke Tanaka, Renesas Electronics Corp. (Japan)
Takao Tamura, Renesas Electronics Corp. (Japan)
Masashi Fujimoto, Renesas Electronics Corp. (Japan)
Kyoichi Tsubata, Renesas Electronics Corp. (Japan)
Naka Onoda, Renesas Electronics Corp. (Japan)
Kiyoshi Fujii, Renesas Electronics Corp. (Japan)

Published in SPIE Proceedings Vol. 8683:
Optical Microlithography XXVI
Will Conley, Editor(s)

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