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Proceedings Paper

Determination of effective width of resist lines by correlation of develop inspect and final inspect CD measurement data
Author(s): J. Kevin McConathy; Ralph Stepp
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Paper Abstract

The objective in making CD measurements at the develop inspect (DI) level is to infer the eventual size of the post etch pattern. Currently this is done by subtracting a factor, often referred to as an "etch bias", from the DI or resist measurement. However, as geometries have grown smaller and design rules have tightened, this technique has proven unreliable. This is due, in part, to variations in the resist side-wall slope from pattern to pattern. Given two resist lines of equal base width, the line with a relatively steep slope will render a wider line at final inspection than a line with a lesser slope. In such cases, use of fixed etch bias factors has obvious drawbacks. The ability to analyze the topographical proffle of resist materials, in a non-destructive manner, is vital in determining the effective width of the resist line. An algorithm has been developed which, given a secondary electron video proffle, can characterize resist side-wall slope as well as measure line width. Combining this data with the final-inspect CD measurement from the same site, and repeating the process on multiple sites and multiple wafers, a relational trend between slope and etch bias (see fig 1) can be described. Using this data, it is possible to generate a dynamic etch bias which will change depending on variations in resist side-wall slope.

Paper Details

Date Published: 1 June 1990
PDF: 5 pages
Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); doi: 10.1117/12.20068
Show Author Affiliations
J. Kevin McConathy, Nanometrics, Inc. (United States)
Ralph Stepp, Sematech Inc. (United States)


Published in SPIE Proceedings Vol. 1261:
Integrated Circuit Metrology, Inspection, and Process Control IV
William H. Arnold, Editor(s)

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