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Proceedings Paper

Methodology to reduce chronic defect mechanisms in semiconductor processing
Author(s): Timothy W. Ecton; Kenneth G. Frazee
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Paper Abstract

This paper docuitents a structur approach to defect elimination in seiiiccructor processing. Classical problem solving techniques were used to logically guide the defect rIuction effort. tfect infontation was gatherei using an automated wafer inspection systeaii ar defects were classifi&1 by production workers on a rete review station. This approach distiruishe actual causes from several probable causes. A process change has reduc the defect mechanism. This methodology was applied to ruce !IEFWN' perfluoroalkoxy (PFA) particles in a one micron semiccructor process. Electrical test structures identified a critical layer where yield loss was occurring. An audit procedure was establishi at this layer arx defects were c1assifi into broad cateories. Further breakout of defect t'pes by appearance was necessaxy to construct a meaningful Pareto chart ard identify the xist fr&ijiently occurring fatal defect. The critical process zone was segmented using autaat wafer inspection to isolate the step causing the defect. An IshiJcawa or cause-effect diagram was construct with input from process engineers to outline all possible causes of the defect. A nest probable branch was selected for investigation arxi pursued until it became clear that this branch was not related to the cause. At this point, new ideas were sought from a sister production facility. ring the visit a breakthrough irxicat& a different path ar ultiltiately lead to identifying the source of the defect. A process change was implemented. An evaluation of the change she1 a substantial decrease in defect evel. rther efforts to eliminate the defect srce are in rogres.

Paper Details

Date Published: 1 June 1990
PDF: 13 pages
Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); doi: 10.1117/12.20064
Show Author Affiliations
Timothy W. Ecton, AT&T Microelectronics (United States)
Kenneth G. Frazee, AT&T Microelectronics (United States)

Published in SPIE Proceedings Vol. 1261:
Integrated Circuit Metrology, Inspection, and Process Control IV
William H. Arnold, Editor(s)

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