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Proceedings Paper

VLSI architecture for high-speed image reconstruction: considerations for a fixed-point architecture
Author(s): Iskender Agi; Paul J. Hurst; K. Wayne Current; Eric Shieh; Stephen G. Azevedo; Gary E. Ford
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Paper Abstract

The amount of data generated by computed tomography (CT) scanners is enormous, making the image reconstruction operation slow, especially for 3-D and limited-data scans requiring iterative algorithms. The inverse Radon transform, commonly used for CT image reconstructions from projections, and the forward Radon transform are computationally burdensome for single-processor computer architectures. Fortunately, the forward Radon transform and the back projection operation (involved in the inverse Radon transform) are easily calculated using a parallel pipelined processor array. Using this array the processing time for the Radon transform and the back projection can be reduced dramatically. This paper describes a unified, pipelined architecture for an integrated circuit that computes both the forward Radon transform and the back projection operation at a 10 MHz data rate in a pipelined processor array. The trade-offs between computational complexity and reconstruction error of different interpolation schemes are presented along with an evaluation of the architecture's noise characteristics due to finite word lengths. The fully pipelined architecture is designed to reconstruct 1024 pixel by 1024 pixel images using up to 1024 projections over 180 degrees. The chip contains three pipelined data-paths, each five stages long, and uses a single multiplier.

Paper Details

Date Published: 1 July 1990
PDF: 14 pages
Proc. SPIE 1246, Parallel Architectures for Image Processing, (1 July 1990); doi: 10.1117/12.19564
Show Author Affiliations
Iskender Agi, Univ. of California/Davis (United States)
Paul J. Hurst, Univ. of California/Davis (United States)
K. Wayne Current, Univ. of California/Davis (United States)
Eric Shieh, Univ. of California/Davis (United States)
Stephen G. Azevedo, Lawrence Livermore National Lab. (United States)
Gary E. Ford, Univ. of California/Davis (United States)

Published in SPIE Proceedings Vol. 1246:
Parallel Architectures for Image Processing
Joydeep Ghosh; Colin G. Harrison, Editor(s)

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