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Proceedings Paper

Architectures and design techniques for real-time image processing
Author(s): Peter A. Ruetz
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Paper Abstract

In this paper some of the techniques that have been been employed in the design of a set of high performance (20- 40 MHz) DSP standard products 1,2 are discussed. To support real-time operation, each device has an architecture that is dedicated to the function being performed. The chip set includes video line delays, a 64-tap 12-bit rank value filter, a 1024-tap binary template matcher, a 64-tap 8-bit FIR filter, a 9-tap 60 MHz FIR filter, a histogram and Hough transform processor, an FFT chip set and an object contour tracer.

Paper Details

Date Published: 1 July 1990
PDF: 9 pages
Proc. SPIE 1246, Parallel Architectures for Image Processing, (1 July 1990); doi: 10.1117/12.19563
Show Author Affiliations
Peter A. Ruetz, LSI Logic Corp. (United States)


Published in SPIE Proceedings Vol. 1246:
Parallel Architectures for Image Processing
Joydeep Ghosh; Colin G. Harrison, Editor(s)

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