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Proceedings Paper

CCD/CMOS process for integrated image acquisition and early vision signal processing
Author(s): Craig L. Keast; Charles G. Sodini
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Paper Abstract

The development of technology which integrates a four phase, buried-channel CCD in an existing 1.75 micron CMOS process is described. The four phase clock is employed in the integrated early vision system to minimize process complexity. Signal corruption is minimized and lateral fringing fields are enhanced by burying the channel. The CMOS process for CCD enhancement is described, which highlights a new double-poly process and the buried channel, and the integration is outlined. The functionality and transfer efficiency of the process enhancement were appraised by measuring CCD shift registers at 100 kHz. CMOS measurement results are presented, which include threshold voltages, poly-to-poly capacitor voltage and temperature coefficients, and dark current. A CCD/CMOS processor is described which combines smoothing and segmentation operations. The integration of the CCD and the CMOS processes is found to function due to the enhancement-compatible design of the CMOS process and the thorough employment of CCD module baseline process steps.

Paper Details

Date Published: 1 July 1990
PDF: 10 pages
Proc. SPIE 1242, Charge-Coupled Devices and Solid State Optical Sensors, (1 July 1990); doi: 10.1117/12.19448
Show Author Affiliations
Craig L. Keast, Massachusetts Institute of Technology (United States)
Charles G. Sodini, Massachusetts Institute of Technology (United States)


Published in SPIE Proceedings Vol. 1242:
Charge-Coupled Devices and Solid State Optical Sensors
Morley M. Blouke, Editor(s)

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