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Proceedings Paper

Design of a CCD focal-plane codec preprocessor for lossless image compression
Author(s): Sabrina E. Kemeny; H. E. Meadows; Eric R. Fossum
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Paper Abstract

The paper presents the design of a CCD-based codec preprocessor (CP) integrated with an areal imager. 3 x 3 pixel neighborhood blocks, where the center pixel arrives first, are utilized for the lossless compression algorithm in the image coding scheme. A 256 x 256 buried-channel frame transfer device with 15 x 15 square microns pixels is employed as the imager. The neighborhood reconstruction is effected by means of both row regrouping and pixel resequencing operations. Four designs for CCD CP chips are described: two hybridized to the imager array, and two integrated with the imager. The chips operate at a 30 Hz frame rate with power dissipation at less than 10 uW. The size of the hybrid chips is 2.5 x 5.5 sq mm, and the focal-plane chips' CPs require an area of 250 x 400 square microns. The CPs provide differential output appropriate for lossless coding and compression to off-chip electronics when reorganization of the image data into local 3 x 3 neighborhood blocks is complete.

Paper Details

Date Published: 1 July 1990
PDF: 8 pages
Proc. SPIE 1242, Charge-Coupled Devices and Solid State Optical Sensors, (1 July 1990); doi: 10.1117/12.19443
Show Author Affiliations
Sabrina E. Kemeny, Columbia Univ. (United States)
H. E. Meadows, Columbia Univ. (United States)
Eric R. Fossum, Columbia Univ. (United States)

Published in SPIE Proceedings Vol. 1242:
Charge-Coupled Devices and Solid State Optical Sensors
Morley M. Blouke, Editor(s)

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