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Proceedings Paper

Two chip ACR-NEMA datalink/physical layer implementation
Author(s): Wayne Thornton DeJarnette
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Paper Abstract

A high performance ACR-NEMA computer interface board for the IBM PC/AT bus will be described. The interface board (AT/NSIF) implements the transport/network thru physical layers of the R-NEW standard. The interface board also supplies a session layer mapping function. The session layer mapping function, the transport/network layer protocol and the datalink layer protocol are implented via an on board microprocessor and resident firmware. The interface board makes use of a pair of gate arrays to implement the datalink frame checksum calculation and the physical layer protocol. The two gate array datalink/physical layer implementation will be described. One gate array interfaces the ACR-NEMA EIA-485 transceivers to high speed buffer memory. This gate array, the Datalink/Physical Layer Pipeline Processor (DLPP), is responsible for the ACR-NEMA physical layer word transfer protocol as well as the physical layer parity calculation. The DLPP also handles the datalink layer checksum calculation in real time. The second gate array, the Datalink/Physical Layer Controller (DLC), contains control and status registers for controlling and monitoring the DLPP. The PLC is also responsible for managing the CR-NEM physical layer interface arbitration. Performance measurements for the Datalink/Physical Layer Pipeline Processor will be detailed. AT/PASIF board level point to point communication performance measurements will be described.

Paper Details

Date Published: 1 August 1990
PDF: 12 pages
Proc. SPIE 1234, Medical Imaging IV: PACS Systems Design and Evaluation, (1 August 1990); doi: 10.1117/12.18967
Show Author Affiliations
Wayne Thornton DeJarnette, DeJarnette Research Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 1234:
Medical Imaging IV: PACS Systems Design and Evaluation
Samuel J. Dwyer; R. Gilbert Jost, Editor(s)

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