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Proceedings Paper

Defect pattern analysis and evaluation of printed circuit boards
Author(s): Masayasu Ito; Isao Fujita; Yoshinori Takeuchi
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Paper Abstract

Recent manufacturing technologies require an automatic inspection system instead of human verification. This is true for the analysis of printed circuit boards with complex conductor patterns and fine pitches. This paper presents a methodology for an automatic inspection and an evaluation of printed circuit boards. We use here topological information on the conductors and insulators of boards. It incorporates a feature graph consisting of skeletons with several types of nodes and branches, locations and others. Inspection is performed by comparing the standard graph created from CAD data with the inspection graph of printed circuit boards. We will discuss fundamental but important preprocessing of optical image, optimum setting of necessary parameters for comparison, and a fast comparison method using variable-length inspection points.

Paper Details

Date Published: 3 October 1994
PDF: 12 pages
Proc. SPIE 2347, Machine Vision Applications, Architectures, and Systems Integration III, (3 October 1994); doi: 10.1117/12.188732
Show Author Affiliations
Masayasu Ito, Tokyo Univ. of Agriculture and Technology (Japan)
Isao Fujita, Tokyo Univ. of Agriculture and Technology (Japan)
Yoshinori Takeuchi, Tokyo Univ. of Agriculture and Technology (Japan)


Published in SPIE Proceedings Vol. 2347:
Machine Vision Applications, Architectures, and Systems Integration III
Bruce G. Batchelor; Susan Snell Solomon; Frederick M. Waltz, Editor(s)

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