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Proceedings Paper

Silicided versus nonsilicided gate technology for submicron CMOS ACIC applications
Author(s): Eric Johnson; Edward Nowak; Chung Wang
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Paper Abstract

This study is a follow-up to earlier work comparing a 0.6 micron, 5 V silicided gate process to a non-silicided process including variations in 'wet' (delute steam) oxidation anneal conditions evaluated for process simplicity. The present data compares various 'dry' (oxygen only) anneal oxidation conditions with previously demonstrated baseline silicided and non-silicided (poly only) gate processes using combinations of nitrogen anneals and deposited oxides. The dry oxidation anneals prevented excessive gate oxide thickening at the gate edge found previously with wet oxidation. Dry oxidation led to minimal LDD overlap and minimal Idsat changes relative to either the silicided gate baseline or a non-silicided gate using thermal TEOS depositions and nitrogen anneals. Reliability data for the non-silicided dry oxidation anneals is included in this study. The non-silicided gate technology, either with dry oxidation anneals or with a deposited cap oxide gate structure and nitrogen anneals, produced hot-electron and gate oxide breakdown results comparable to the silicided gate baseline with potentially attractive manufacturing advantages.

Paper Details

Date Published: 16 September 1994
PDF: 7 pages
Proc. SPIE 2336, Manufacturing Process Control for Microelectronic Devices and Circuits, (16 September 1994); doi: 10.1117/12.186787
Show Author Affiliations
Eric Johnson, VLSI Technology Inc. (United States)
Edward Nowak, VLSI Technology Inc. (United States)
Chung Wang, VLSI Technology Inc. (United States)


Published in SPIE Proceedings Vol. 2336:
Manufacturing Process Control for Microelectronic Devices and Circuits
Anant G. Sabnis, Editor(s)

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