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Proceedings Paper

Defect isolation using electron-beam probing RIE in multilevel high-density ASICs
Author(s): Sharad Prasad; Grant Lindberg; Hong Zhang
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Paper Abstract

Electron beam probing is a powerful technique for analyzing failures in integrated circuits. This technique has been modified and different automation techniques such as IDA, FACE and analysis techniques have been added to analyze complex circuits. However, with increasingly small geometries and multi levels of metallization none of these techniques can work satisfactorily unless the e-beam can manage to obtain signals from the bottom metal layers. In this paper we present a successful method which has been used with a 4 metal layer process to probe up to metal 1. As geometries shrink it is absolutely necessary that after removal of intermediate dielectric no residue remains, otherwise there could be intermetallic shorts. RIE has been used successfully for failure analysis. In this paper we present a method of selectively removing inter-metal dielectric using RIE and doing e-beam probing. RIE is so optimized that there is no `RIE grass' and 3/4 metal layer ASICs with 0.5 micrometers minimum geometry function electrically. Using special fixtures and optimizing the gas flow, gas pressure and power, the removal of dielectric was so optimized that: (1) The amount of intermediate dielectric removed can be varied just by time. This is necessary to stay compatible with different technologies using different metal layers and dielectric thickness. (2) There is no `RIE grass.' (3) Devices function electrically even after removal of intermediate oxide and metal 1 is exposed. After the dielectric is removed the parts are exercised electrically using an ATE for instance ASIX or LT and measurements are taken using the e- beam tester IDS5000+. This paper discusses in detail the RIE process, fixtures, and the usage of the e-beam tester on multilayer 0.5 micrometers process.

Paper Details

Date Published: 14 September 1994
PDF: 7 pages
Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186770
Show Author Affiliations
Sharad Prasad, LSI Logic Corp. (United States)
Grant Lindberg, LSI Logic Corp. (United States)
Hong Zhang, LSI Logic Corp. (United States)


Published in SPIE Proceedings Vol. 2334:
Microelectronics Manufacturability, Yield, and Reliability
Barbara Vasquez; Hisao Kawasaki, Editor(s)

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