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Proceedings Paper

Practical application of a wafer-level reliability control program
Author(s): Jeff S. May; Javier Saenz; Hoang Huy Hoang
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Paper Abstract

Wafer level reliability (WLR) was envisioned as an upstream tool to be applied within the wafer fab process to avoid or detect reliability problems before they can reach the fmished product. To demonstrate a practical application of this approach, the development, execution and results of a WLR qualification and production control plan for an advanced, sub-micron, triple-level metal CMOS process is provided. The WLR qualification evaluated the following reliability concerns: oxygen precipitation, contact integrity, hot carrier reliability, mobile ion contamination, dielectric integrity, electromigration, stress voiding, via integrity, and corrosion susceptibility. The production control plan describes a statistical process control (SPC) program which monitors input process parameters and electrical parameters measured prior to fmal test that are used to disposition lots. Keywords: wafer level reliability, building-in reliability, designing-in reliability, process control, qualification.

Paper Details

Date Published: 14 September 1994
PDF: 10 pages
Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186766
Show Author Affiliations
Jeff S. May, SGS-Thomson Microelectronics, Inc. (United States)
Javier Saenz, SGS-Thomson Microelectronics, Inc. (United States)
Hoang Huy Hoang, SGS-Thomson Microelectronics, Inc. (United States)


Published in SPIE Proceedings Vol. 2334:
Microelectronics Manufacturability, Yield, and Reliability
Barbara Vasquez; Hisao Kawasaki, Editor(s)

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