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Proceedings Paper

Statistical metrology for interlevel dielectric thickness variation
Author(s): Duane S. Boning; Tinaung Maung; James E. Chung; Keh-Jeng Chang; Soo-Young Oh; Dirk Bartelink
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Paper Abstract

Statistical metrology seeks to assess the sources and magnitude of variation in semiconductor manufacturing. The methodology emphasizes electrical measurements resulting from short process flows, statistical design of experiments and analysis of data, and close coupling to technology computer aided design tools for the interpretation of data. In this paper, we apply statistical metrology to interlevel dielectric thickness variation. Capacitive test structures, in conjunction with resistive line width structures and two-dimensional capacitance simulations, are used to estimate ILD thickness for a variety of layout and process factors in a poly-metal BPSG planarization process. The methodology is successful in highlighting the key factors, including underlying structure line width spacing,and finger length that impact ILD thickness. Future work will examine other planarization processes, including chemical mechanical polishing.

Paper Details

Date Published: 14 September 1994
PDF: 12 pages
Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186764
Show Author Affiliations
Duane S. Boning, Massachusetts Institute of Technology (United States)
Tinaung Maung, Massachusetts Institute of Technology (United States)
James E. Chung, Massachusetts Institute of Technology (United States)
Keh-Jeng Chang, Hewlett-Packard Co. (United States)
Soo-Young Oh, Hewlett-Packard Co. (United States)
Dirk Bartelink, Hewlett-Packard Co. (United States)


Published in SPIE Proceedings Vol. 2334:
Microelectronics Manufacturability, Yield, and Reliability
Barbara Vasquez; Hisao Kawasaki, Editor(s)

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