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Proceedings Paper

Reliability simulator for improving IC manufacturability
Author(s): Mohamod S. Moosa; Kelvin F. Poole
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Paper Abstract

A Monte-Carlo reliability simulator for integrated circuits that incorporates the effects of process-flaws, material properties, the mask layout and use-conditions for interconnects is presented. The mask layout is decomposed into distinct objects, such as contiguous metal runs, vias and contacts, for which user-defined cumulative distribution functions (cdfs) are used for determining the probability of failure. These cdfs are represented using a mixture of defect- related and wearout-related distributions. The failure distributions for nets, which are sets of interconnected layout objects, are obtained by combining the distributions of their component objects. System reliability is obtained by applying control variate sampling to the reliability network which is comprised of all nets. The effects of series, parallel and k-out-of-n substructures within the reliability network are accounted for. A Bayesian approach to incorporating burn-in data with simulated estimates is also presented. A program that interfaces directly with commercially used CAD software has been implemented. Results provide a qualitative verification of the methodology and show that predictions which incorporate failures due to process flaws are significantly more pessimistic than those obtained by following current practice.

Paper Details

Date Published: 14 September 1994
PDF: 8 pages
Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186760
Show Author Affiliations
Mohamod S. Moosa, Clemson Univ. (United States)
Kelvin F. Poole, Clemson Univ. (United States)


Published in SPIE Proceedings Vol. 2334:
Microelectronics Manufacturability, Yield, and Reliability
Barbara Vasquez; Hisao Kawasaki, Editor(s)

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