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Proceedings Paper

Reduction of low-level current leakage in CMOS devices
Author(s): George Y. Kong; Jerry T. Healey
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Paper Abstract

The continuing trend toward smaller device feature sizes and the increasing demand for ever greater levels of reliability has resulted in an increased level of interest in the problem of low- level current leakage. Not only do previously acceptable levels of leakage become problematic at smaller device geometries, but a low-level of current leakage is a good overall indicator of device defectivity, and thus reliability. Experiments have been conducted in which a specific HF clean was observed to significantly reduce leakage in polysilicide CMOS devices. It is theorized that the HF clean removes contaminants located in the top 100 angstrom of the gate oxide over the source/drain regions. These contaminants are driven into the gate oxide during subsequent thermal processing and result in the creation of low-level current leakage sites. This paper describes the character of a current leakage problem encountered on a polysilicide CMOS device which has an extremely low current leakage specification (< 600 nA). The development and optimization of a process modification involving screen oxide and an HF clean which eliminated the source of low-level current leakage is presented. This process modification is currently in use in an industrial environment, is robust, reliable, and has resulted in a substantial increase in yield.

Paper Details

Date Published: 14 September 1994
PDF: 15 pages
Proc. SPIE 2334, Microelectronics Manufacturability, Yield, and Reliability, (14 September 1994); doi: 10.1117/12.186748
Show Author Affiliations
George Y. Kong, Motorola (United States)
Jerry T. Healey, Motorola (United States)


Published in SPIE Proceedings Vol. 2334:
Microelectronics Manufacturability, Yield, and Reliability
Barbara Vasquez; Hisao Kawasaki, Editor(s)

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