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Proceedings Paper

Low-cost laser scanning technique for CMOS latchup detection
Author(s): Donald L. Parker
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Paper Abstract

Since the CMOS Latchup phenomena is due to parasitic bipolar elements in the monolithic structure, this failure potential is always present and may return with each new circuit design or shrink of a proven design. Industry standard tests do not always identify latchup problems and/or pinpoint the exact latchup sites. laser scanning during electrical test has been shown to dot both, however, the expense of existing laser scanning systems has prevented widespread application of the procedure. This paper describes a system which features very low cost components including a semiconductor laser diode and an acoustic detection scheme which allows detection of all sites and a qualitative estimate of latchup susceptibility. if routinely used, the method could perhaps allow a smoother evolution of design rules.

Paper Details

Date Published: 14 September 1994
PDF: 7 pages
Proc. SPIE 2337, Optical Characterization Techniques for High-Performance Microelectronic Device Manufacturing, (14 September 1994); doi: 10.1117/12.186650
Show Author Affiliations
Donald L. Parker, Texas A&M Univ. (United States)

Published in SPIE Proceedings Vol. 2337:
Optical Characterization Techniques for High-Performance Microelectronic Device Manufacturing
Jagdish P. Mathur; John K. Lowell; Ray T. Chen, Editor(s)

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