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Proceedings Paper

Spin-on-glass (SOG) partial etch-back planarization process with 0.4-um gap filling ability
Author(s): Maurizio Bacchetta; Chiara Zaccherini
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Paper Abstract

Multilevel interconnection technology requires higher and higher planarization performances, to allow the use of three or more interconnection layers. A high planarization degree is in fact mandatory to avoid process degradation with the increasing number of interconnection layers. The cold planarization scheme, most widely used nowadays, consists in the SOG (spin on glass) deposition, for gap filling, followed by the SOG partial etch-back (PEB) process to remove SOG from the top of metal structures, where VIAs are to be opened. This type of process is, however, limited by SOG gap filling capability. In this paper a new semi-integrated SOG based inter-metal dielectric (IMD) planarization process is shown, capable of filling metal spaces down to 0.4 micrometers , and providing a good long-range planarization degree. The possibility of extending SOG based planarization processes to .35 micrometers generation devices has been successfully demonstrated with the introduction of an oxide tapering process just before SOG coating. The tapering consists of an argon sputter etch, integrated in the same equipment where the first PECVD oxide deposition is performed. Different argon etch conditions were evaluated to obtain the optimal oxide shape. The planarization process was completed with an integrated partial SOG etch-back and PECVD TEOS cap layer deposition process. Results are presented in terms of SOG filling and planarization degree data as a function of gap width and aspect ratio and in terms of process defectivity.

Paper Details

Date Published: 9 September 1994
PDF: 9 pages
Proc. SPIE 2335, Microelectronics Technology and Process Integration, (9 September 1994); doi: 10.1117/12.186064
Show Author Affiliations
Maurizio Bacchetta, SGS-Thomson Microelectronics, Inc. (Italy)
Chiara Zaccherini, SGS-Thomson Microelectronics, Inc. (Italy)

Published in SPIE Proceedings Vol. 2335:
Microelectronics Technology and Process Integration
Fusen E. Chen; Shyam P. Murarka, Editor(s)

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