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Proceedings Paper

Analysis and modeling of submicron drain-offset polysilicon thin film transistors (TFTs)
Author(s): John Damiano; Le-Tien Jung; Sanjay K. Banerjee; S. Batra; M. Manning; C. Dennison
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Paper Abstract

Drain-offset polysilicon thin-film transistors (DO-TFTs) with different offset lengths and doping were fabricated and characterized. The grain boundary trap states in the offset region strongly influence the electrical behavior of the TFTs. The on state current is influenced by the grain microstructure in the drain-offset region and channel region, as evidenced by the drain current activation energy measurements. The off state leakage current is dominated by the generation of carriers in the drain offset depletion region, where the trap states serve as generation/recombination centers and reduce the barrier for tunneling. A model based on the Poole-Frenkel effect and thermionic field emission was developed to account for the leakage mechanism.

Paper Details

Date Published: 9 September 1994
PDF: 6 pages
Proc. SPIE 2335, Microelectronics Technology and Process Integration, (9 September 1994); doi: 10.1117/12.186060
Show Author Affiliations
John Damiano, Univ. of Texas/Austin (United States)
Le-Tien Jung, Univ. of Texas/Austin (United States)
Sanjay K. Banerjee, Univ. of Texas/Austin (United States)
S. Batra, Micron Semiconductor, Inc. (United States)
M. Manning, Micron Semiconductor, Inc. (United States)
C. Dennison, Micron Semiconductor, Inc. (United States)


Published in SPIE Proceedings Vol. 2335:
Microelectronics Technology and Process Integration
Fusen E. Chen; Shyam P. Murarka, Editor(s)

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