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Proceedings Paper

Architecture and modeling of a parallel digital processor based image processing system
Author(s): David Andrew Hartley; Shirish P. Kshirsagar
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Paper Abstract

The paper describes an image processing system which uses both shared memory and message passing. Shared memory is used in conjunction with a high speed parallel bus to transfer image data; message passing is used for general inter-processor communication. A prototype system based upon the Texas Instruments TMS320C40 digital signal processor is currently in the final stages of construction. A Petri Net model of the communication aspects of the TMS320C40 processor has been developed. Features of the Petri Net software are discussed and the raw communication performance of the TMS320C40 shown. The modeling of a four and sixteen processor system applied to 2D FFT transforms is described.

Paper Details

Date Published: 16 September 1994
PDF: 9 pages
Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994); doi: 10.1117/12.185937
Show Author Affiliations
David Andrew Hartley, Liverpool John Moores Univ. (United Kingdom)
Shirish P. Kshirsagar, Liverpool John Moores Univ. (United Kingdom)


Published in SPIE Proceedings Vol. 2308:
Visual Communications and Image Processing '94
Aggelos K. Katsaggelos, Editor(s)

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