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Proceedings Paper

Single-chip highly parallel architecture for image processing applications
Author(s): Johannes Kneip; Karsten Roenner; Peter Pirsch
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Paper Abstract

For real-time implementation of image processing applications a general purpose Single Instruction/Multiple Data multiprocessor is proposed. The processor consists of an array of data paths, embedded in a two stage memory hierarchy, built of a shared memory with conflict free parallel access in shape of a matrix and a local cache, autonomously addressable by the data paths. The array is controlled by a Reduced Instruction Set Controller with load/store architecture and a fixed field coded very long instruction word. A six stage instruction pipeline leads to a low cycle time of the processor. To provide the necessary flexibility of the array processor even for the parallel processing of complex algorithms, a three stage autonomous controlling hierarchy for the processing units has been implemented. This concept leads to a high level language programmable homogeneous architecture with sustained performance on a wide spectrum of image processing algorithms. For an array of 16 processing units at 100 MHz clock frequency, an arithmetic processing power of 2.0 - 2.4 gigaoperations per second for several algorithms is achieved.

Paper Details

Date Published: 16 September 1994
PDF: 12 pages
Proc. SPIE 2308, Visual Communications and Image Processing '94, (16 September 1994); doi: 10.1117/12.185932
Show Author Affiliations
Johannes Kneip, Univ. Hannover (Germany)
Karsten Roenner, Univ. Hannover (Germany)
Peter Pirsch, Univ. Hannover (Germany)


Published in SPIE Proceedings Vol. 2308:
Visual Communications and Image Processing '94
Aggelos K. Katsaggelos, Editor(s)

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