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Proceedings Paper

Fault avoidance for optical logic arrays and regular free-space interconnects
Author(s): Miles J. Murdocca
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Paper Abstract

An optical computing model is described that makes use of arrays of optical logic gates interconnected in free space with regular connection patterns. An advantage of this approach is that interconnection complexity is moved to free space which is virtually free of faults. A cost of this approach is that the regular interconnection patterns restrict connectivity to the extent that a number of logic gates are inaccessible. Methods are described for moving the operational, inaccessible logic gates into the positions of faulty logic gates. The result is that the effective yields of optical logic arrays are increased and device processing tolerances are relaxed.

Paper Details

Date Published: 1 July 1990
PDF: 7 pages
Proc. SPIE 1215, Digital Optical Computing II, (1 July 1990); doi: 10.1117/12.18054
Show Author Affiliations
Miles J. Murdocca, Rutgers Univ. (United States)


Published in SPIE Proceedings Vol. 1215:
Digital Optical Computing II
Raymond Arrathoon, Editor(s)

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