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Proceedings Paper

Process engineering: overview of wafer fab process engineering dealing with equipment, processes, and control techniques to meet the SIA road map
Author(s): Nigel R. Farrar
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Paper Abstract

Lithography process control is critical for achieving good yield from increasingly complex generations of integrated circuits. Linewidth and overlay control over large die areas are required with smaller errors than ever before. Increasingly complex and expensive equipment and processes are needed to meet these goals. This paper will give an overview of the process engineering issues primarily associated with the 0.35 micron and 0.25 micron generations of integrated circuits. Linewidth control, in particular, will be covered in some detail with emphasis on the effect of the different contributions to focus and exposure variations during patterning. The influence of incoming wafer process variations on the process design for different layers will be described. The challenges of defect density control and throughput and cost control using advanced equipment and processes will be outlined. Mask layout and fabrication issues relating to improved wafer process margins will be discussed. The impact of metrology limitations on the ability to control lithography processes will be described.

Paper Details

Date Published: 1 January 1994
PDF: 24 pages
Proc. SPIE 10273, 64-to 256-Megabit Reticle Generation: Technology Requirements and Approaches: A Critical Review, 1027307 (1 January 1994); doi: 10.1117/12.177439
Show Author Affiliations
Nigel R. Farrar, Hewlett-Packard Co. (United States)


Published in SPIE Proceedings Vol. 10273:
64-to 256-Megabit Reticle Generation: Technology Requirements and Approaches: A Critical Review
Gregory K. Hearn, Editor(s)

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