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Proceedings Paper

Cleaning and pelliclization
Author(s): Susan V. Daugherty
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Paper Abstract

The final step in the reticle manufacturing process takes place in the Cleaning and Pelliclization Area. Traditionally, this area covers reticle clean, pellicle mount, and particle inspection. Pellicles are used to protect the clean reticle: the pellicle membrane holds air borne particles away from the surface of the reticle, thus out of the focal plane, so the particles won't print on the wafer. The pellicle surface can tolerate larger particles than the reticle surface, making the reticle/pellicle combination more reliable in wafer fab.

In the past, the Cleaning and Pelliclization Area's main concern has been "soft" defects. Soft defects can be defined as any defect that can be removed by cleaning, such as particles, contamination, residue, stains, etc. The inspection tools used to verify the Cleaning and Pelliclization process have been focused on soft defect detection, i.e. particle inspection systems. Hard defects then, are defined as any defect involving the photomask substrate, such as missing or extra chrome, glass flaws, or scratches. The increased use of automation in the Cleaning and Pelliclization process forces concern and inspection for hard defects.

The only important specification in the Cleaning and Pelliclization process is zero defects, at a given size level. The given size level is complicated by the various locations of concern: the pellicle surfaces, the pattern side surfaces, and the glass side surfaces. As die sizes continue to increase, reticles have fewer dies. This places a tremendous responsibility on the Cleaning and Pelliclization area to deliver a reticle with zero printable killer defects, and zero defects that may move from a non-printing position into a printing position.

This paper will first cover defect definitions, locations, specifications, and the current status of the Cleaning and Pelliclization process in Production today, the process geared for 16-megabit DRAM specifications. The general process flow and the current trends in processing and equipment will be reviewed. Next, the process for the 64-megabit DRAM's, currently in development mode, will be discussed. Finally, the future projections for the needs in the Cleaning and Pelliclization Area to meet the challenges for the phase shift mask (PSM) and DUV technologies, and the 256-megabit DRAM process will be reviewed.

Paper Details

Date Published: 1 January 1994
PDF: 12 pages
Proc. SPIE 10273, 64-to 256-Megabit Reticle Generation: Technology Requirements and Approaches: A Critical Review, 102730D (1 January 1994); doi: 10.1117/12.177433
Show Author Affiliations
Susan V. Daugherty, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 10273:
64-to 256-Megabit Reticle Generation: Technology Requirements and Approaches: A Critical Review
Gregory K. Hearn, Editor(s)

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