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Proceedings Paper

23,000 frame-per-second 256x128 camera with digital control
Author(s): Jack J. Lula; Mike Miethig; David J. Litwiller; Brian C. Doody; William D. Washkurak; Savvas G. Chamberlain
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Paper Abstract

This paper describes the design of a 10 bit, 23,000 frame per second camera with digital control. The camera is based around a 64-tap 256 X 128 element interline transfer CCD with a current mode output. Readout is at 12 MHz per tap for an aggregate data rate of 768 megapixels per second. Sixteen MHz operation (30,000 frames per second) is possible with reduced performance. Digitization is to 10 bits with 8.5 bits rms effective. The signal processing chain allows for digital control of the analog gain and features a feedback loop to maintain offset stability. Linearity of the processing chain is 0.2%. Additional features included digital control of the integration time and readout rate, and digital compensation of light level. Digitized data is transmitted over high speed serial links to a remote rack that emulates the target processing system. An automated analysis system is able to exercise the system and measure performance characteristics.

Paper Details

Date Published: 5 May 1994
PDF: 12 pages
Proc. SPIE 2173, Image Acquisition and Scientific Imaging Systems, (5 May 1994); doi: 10.1117/12.175168
Show Author Affiliations
Jack J. Lula, DALSA Inc. (Canada)
Mike Miethig, DALSA Inc. (Canada)
David J. Litwiller, DALSA Inc. (Canada)
Brian C. Doody, DALSA Inc. (Canada)
William D. Washkurak, DALSA Inc. (Canada)
Savvas G. Chamberlain, DALSA Inc. (Canada)


Published in SPIE Proceedings Vol. 2173:
Image Acquisition and Scientific Imaging Systems
Helen C. Titus; Amir Waks, Editor(s)

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