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Proceedings Paper

Parallel butterfly algorithm and VLSI architectures for image decorrelation
Author(s): Tinku Acharya; Amar Mukherjee
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Paper Abstract

We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the- art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favorably comparable to the JPEG baseline lossless image compression schemes. We also discuss the parallelization issues of the JPEG baseline standard still compression schemes and their difficulties.

Paper Details

Date Published: 2 May 1994
PDF: 11 pages
Proc. SPIE 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies, (2 May 1994); doi: 10.1117/12.174967
Show Author Affiliations
Tinku Acharya, Univ. of Central Florida (United States)
Amar Mukherjee, Univ. of Central Florida (United States)


Published in SPIE Proceedings Vol. 2187:
Digital Video Compression on Personal Computers: Algorithms and Technologies
Arturo A. Rodriguez, Editor(s)

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