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Proceedings Paper

Effect of resist processes on dimensional control of submicron polysilicon gate structures
Author(s): Brian Martin; Graham G. Arthur
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Paper Abstract

Conventional resist, without and with an underlying anti-reflective coating, and a dyed resist are used to calibrate the sub-micron dimensional control across a 6 inch diameter wafer coated with LPCVD polysilicon, as used in the manufacture of advanced CMOS devices by i-line technology. Results are referenced to the dimensional control measured for the same resist process on bare silicon test wafers. The effect of variable substrate reflectivity, with respect to the different resist processes, is thus assessed. Intra-field dimensional control over typical circuit topography is also measured for the same resist processes. Results are related to the amplitude of the linewidth vs resist thickness functions of the appropriate process that are derived from simulations using the SOLID modeling package.

Paper Details

Date Published: 1 May 1994
PDF: 12 pages
Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); doi: 10.1117/12.174157
Show Author Affiliations
Brian Martin, GEC Plessey Semiconductors Ltd. (United Kingdom)
Graham G. Arthur, Rutherford Appleton Lab. (United Kingdom)


Published in SPIE Proceedings Vol. 2196:
Integrated Circuit Metrology, Inspection, and Process Control VIII
Marylyn Hoy Bennett, Editor(s)

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