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Proceedings Paper

Overlay sample plan optimization for the detection of higher order contributions to misalignment
Author(s): Ian D. Fink; Neal T. Sullivan; James S. Lekas
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Paper Abstract

Using a commercially available software package, overlay sample plans were evaluated for use in a 0.5 micrometers manufacturing process. Monitor wafers were patterned using a two layer overlay evaluation reticle set. Known values of both grid and field errors were entered into the stepper during the exposure of the second layer to force a controlled range of misregistration. Extensive overlay measurements were collected from these wafers. These detailed data sets were modeled to define the relationships between distortion coefficients reported by the software and those actually entered into the stepper. Using the modeled distortions obtained from the original data set as the `correct' values of overlay distortion present on the die/wafers, it was possible to model subsets of the original data set to determine the most efficient sample plans for manufacturing. The accuracy and uncertainty of the modeled overlay distortions was found to be dependent on the sample plan, both in terms of the number and location of measurements taken.

Paper Details

Date Published: 1 May 1994
PDF: 11 pages
Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); doi: 10.1117/12.174141
Show Author Affiliations
Ian D. Fink, Digital Equipment Corp. (United States)
Neal T. Sullivan, Digital Equipment Corp. (United States)
James S. Lekas, Digital Equipment Corp. (United States)


Published in SPIE Proceedings Vol. 2196:
Integrated Circuit Metrology, Inspection, and Process Control VIII
Marylyn Hoy Bennett, Editor(s)

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