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Proceedings Paper

Process-induced effects on the intrafield overlay error
Author(s): Young-Mog Ham; Chul-Seung Lee; YoungSik Kim; Dong-Jun Ahn; Soo-Han Choi; YeonSeon Seo; Mark Andrew Merrill
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Paper Abstract

As the design rule of devices continues to shrink, the overlay margin of layer to layer continues to become smaller. Inter-field error of overlay can be compensated by alignment parameters of the exposure system, but intra-field error of overlay is very difficult to change within a field. This paper discusses the intra-field overlay error, especially that caused by oxidation and deposition processes of a metal-oxide-silicon (MOS) integrated circuit device. In an experiment, to analyze process induced affects on the intra-field overlay error of device, we monitored thermal process, film deposition, oxidation, lithography, etching, and implantation process and pursued the trend and sources of intra-field overlay error generated in wafer process. We analyzed the affects of film stress and thermal process by measuring box and box overlay marks using the KLA metrology system at the etch process step.

Paper Details

Date Published: 1 May 1994
PDF: 9 pages
Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); doi: 10.1117/12.174138
Show Author Affiliations
Young-Mog Ham, Hyundai Electronics Industries Co., Ltd. (South Korea)
Chul-Seung Lee, Hyundai Electronics Industries Co., Ltd. (South Korea)
YoungSik Kim, Hyundai Electronics Industries Co., Ltd. (South Korea)
Dong-Jun Ahn, Hyundai Electronics Industries Co., Ltd. (South Korea)
Soo-Han Choi, Hyundai Electronics Industries Co., Ltd. (South Korea)
YeonSeon Seo, KLA Instruments Co. (United States)
Mark Andrew Merrill, KLA Instruments Co. (United States)


Published in SPIE Proceedings Vol. 2196:
Integrated Circuit Metrology, Inspection, and Process Control VIII
Marylyn Hoy Bennett, Editor(s)

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