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Proceedings Paper

0.35-micron DUV lithography for poly gate layer
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Paper Abstract

The evaluation of processes for 0.35 micron poly gate patterning using DUV negative resist is described. The advantages and drawbacks of negative versus positive resist, for linewidth control, are outlined. The necessity of using top or bottom anti-reflective coatings is examined. The performance of the different process schemes is compared, with regard to linewidth control over isolation topography, reflective notching control, line edge roughness, and line length control. Although the negative tone resist showed good process latitude and performed well, with regard to notching behavior, the high transmission of the resist led to unacceptable linewidth variations unless a bottom anti-reflective coating was used.

Paper Details

Date Published: 1 May 1994
PDF: 11 pages
Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); doi: 10.1117/12.174135
Show Author Affiliations
Nigel R. Farrar, Hewlett-Packard Labs. (United States)
Bhanwar Singh, Advanced Micro Devices, Inc. (United States)


Published in SPIE Proceedings Vol. 2196:
Integrated Circuit Metrology, Inspection, and Process Control VIII
Marylyn Hoy Bennett, Editor(s)

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