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Proceedings Paper

Optical and electronic error correction schemes for highly parallel access memories
Author(s): Mark Allen Neifeld; Jerry D. Hayes
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Paper Abstract

We have fabricated and tested an optically addressed, parallel electronic Reed-Solomon decoder for use with parallel access optical memories. A comparison with various serial implementations has demonstrated that for many instances of code block size and error correction capability, the parallel approach is superior from the perspectives of VLSI layout area and decoding latency. The demonstrated Reed-Solomon parallel pipeline decoder operates on 60 bit input words and has been demonstrated at a clock rate of 5 MHz yielding a demonstrated data rate of 300 Mbps.

Paper Details

Date Published: 9 November 1993
PDF: 11 pages
Proc. SPIE 2026, Photonics for Processors, Neural Networks, and Memories, (9 November 1993); doi: 10.1117/12.163604
Show Author Affiliations
Mark Allen Neifeld, Univ. of Arizona (United States)
Jerry D. Hayes, Univ. of Arizona (United States)


Published in SPIE Proceedings Vol. 2026:
Photonics for Processors, Neural Networks, and Memories
Stephen T. Kowel; William J. Miceli; Joseph L. Horner; Bahram Javidi; Stephen T. Kowel; William J. Miceli, Editor(s)

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