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Proceedings Paper

Implementing neural nets on non-ideal analog hardware
Author(s): Leonard Neiberg; David P. Casasent
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Paper Abstract

We consider the implementation of high capacity Ho-Kashyap associative processors on non- ideal optical and analog VLSI systems. Processor non-idealities considered include quantization, non-uniform beam illumination, and nonlinear device characteristics. New training-out techniques to overcome these non-idealities are advanced. We obtain optimal performance in the presence of stochastic noise by proper selection of the processor parameter (sigma) syn. We derive important results that allow us to a priori determine the optimal value of (sigma) syn and the expected recall accuracy P'c without having to simulate the specific processor. We present a new algorithm that allow us to achieve storage near the theoretical maximum capacity (2N, where N is the dimensionality of the input vector) with excellent recall accuracy. Optical laboratory results are included. We achieved storage of 1.5 N with recall accuracy P'c >= 95% with input noise of standard deviation (omega) 1 equals 0.02 present and with optical analog components with 5 bit input accuracy and 8 bit memory matrix accuracy. With higher accuracy analog VLSI components (10 bit input accuracy and 11 bit weight accuracy), we achieve storage of 1.75 N with P'c equals 96.43%.

Paper Details

Date Published: 9 November 1993
PDF: 14 pages
Proc. SPIE 2026, Photonics for Processors, Neural Networks, and Memories, (9 November 1993); doi: 10.1117/12.163598
Show Author Affiliations
Leonard Neiberg, Carnegie Mellon Univ. (United States)
David P. Casasent, Carnegie Mellon Univ. (United States)


Published in SPIE Proceedings Vol. 2026:
Photonics for Processors, Neural Networks, and Memories
Stephen T. Kowel; William J. Miceli; Joseph L. Horner; Bahram Javidi; Stephen T. Kowel; William J. Miceli, Editor(s)

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