Proceedings PaperFault-tolerant array processor for parallel image processing
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Parallel image processing systems with numerous processing elements (PE), connected in local and regular net, must be fault-tolerant for better reliability and better yield when realized by VLSI technology. The fault-tolerant array processor described in this paper has a regular array of simple programmable PEs and a distributed hardware sub-system for selftesting, selfdiagnostics, and selfreconfiguration.