Share Email Print

Proceedings Paper

Fault-tolerant array processor for parallel image processing
Author(s): Oleg V. Podroobny
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Parallel image processing systems with numerous processing elements (PE), connected in local and regular net, must be fault-tolerant for better reliability and better yield when realized by VLSI technology. The fault-tolerant array processor described in this paper has a regular array of simple programmable PEs and a distributed hardware sub-system for selftesting, selfdiagnostics, and selfreconfiguration.

Paper Details

Date Published: 4 November 1993
PDF: 12 pages
Proc. SPIE 1976, High-Definition Video, (4 November 1993); doi: 10.1117/12.161483
Show Author Affiliations
Oleg V. Podroobny, Integral (Russia)

Published in SPIE Proceedings Vol. 1976:
High-Definition Video
Naohisa Ohta, Editor(s)

© SPIE. Terms of Use
Back to Top