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Proceedings Paper

Maximizing run time performance of deployed data flow graphs on a multiprocessor architecture
Author(s): Richard J. Tobias; Peter D. Hunt
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Paper Abstract

This paper discusses a practical solution for supporting the deployment of data flow graphs onto the Loral/Rolm Computer Systems, Inc. vector processing multi-processor architecture. It outlines the support software (both workstation hosted and target system hosted) that is required to design, debug, and maximize deployed data flow graph performance on the multiprocessor architecture. The deployment process guarantees real-time deadlines, minimizes run time scheduling overhead, and minimizes designer partitioning input. It is known that determining effective run time data flow graph node schedules for multi-processor architectures is an NP-complete class of problem not well suited to real-time systems. Loral/Rolm Computer Systems, Inc.'s vector processing toolset recognizes this problem and this paper discusses a prescheduling and pre-assignment approach for partitioning data flow graphs to available hardware resources. In particular the toolset components (which are based upon an enhanced data flow graph language) of workstation pre-assignment, prescheduling, run time gross allocation and local compute element dispatching are discussed in detail.

Paper Details

Date Published: 20 October 1993
PDF: 9 pages
Proc. SPIE 1957, Architecture, Hardware, and Forward-Looking Infrared Issues in Automatic Target Recognition, (20 October 1993); doi: 10.1117/12.161444
Show Author Affiliations
Richard J. Tobias, Loral/Rolm Computer Systems, Inc. (United States)
Peter D. Hunt, Loral/Rolm Computer Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 1957:
Architecture, Hardware, and Forward-Looking Infrared Issues in Automatic Target Recognition
Lynn E. Garn; Lynda Ledford Graceffo, Editor(s)

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