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Proceedings Paper

Heterogeneous multiprocessor architecture for video coding applications
Author(s): Richard Hoffer; Winfried Gehrke; Peter Pirsch
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Paper Abstract

A multiprocessor architecture for compact realizations of video coding applications is presented. The actual standards for video coding e.g. H.261 and MPEG are based on a hybrid coding scheme, which allows parallelization at both data level and task level. The parallelization at data level is performed by distribution of image data among the processors. Each processor works on locally stored image segments. The parallelization at task level is realized inside the processors by functional modules which are adapted to classes of algorithms. The functionality of the modules and the number of their data paths is determined by applying efficiency calculations resulting in a module for motion estimation and a block- level coprocessor for transform and quantization. The controlling and synchronization is accomplished by a programmable module. A hierarchical controlling concept reduces the on- chip control overhead. A chip size of 70 mm2 is estimated for one processor, when using 0.6 micrometers CMOS technology. With an operating frequency of 65 MHz one chip will perform the computations for a full CIF H.261 codec with 30 Hz framerate and motion estimation based on +/-15 pel full search blockmatching algorithm.

Paper Details

Date Published: 29 October 1993
PDF: 8 pages
Proc. SPIE 1977, Video Communications and PACS for Medical Applications, (29 October 1993); doi: 10.1117/12.160486
Show Author Affiliations
Richard Hoffer, Univ. Hannover (Germany)
Winfried Gehrke, Univ. Hannover (Germany)
Peter Pirsch, Univ. Hannover (Germany)


Published in SPIE Proceedings Vol. 1977:
Video Communications and PACS for Medical Applications
Rudy A. Mattheus; Andre J. Duerinckx; Peter J. van Otterloo, Editor(s)

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