Share Email Print

Proceedings Paper

Unifying parametrized VLSI Jacobi algorithms and architectures
Author(s): Ed F. A. Deprettere; Marc Moonen
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Implementing Jacobi algorithms in parallel VLSI processor arrays is a non-trivial task, in particular when the algorithms are parametrized with respect to size and the architectures are parametrized with respect to space-time trade-offs. The paper is concerned with an approach to implement several time-adaptive Jacobi-type algorithms on a parallel processor array, using only Cordic arithmetic and asynchronous communications, such that any degree of parallelism, ranging from single-processor up to full-size array implementation, is supported by a `universal' processing unit. This result is attributed to a gracious interplay between algorithmic and architectural engineering.

Paper Details

Date Published: 1 November 1993
PDF: 9 pages
Proc. SPIE 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV, (1 November 1993); doi: 10.1117/12.160463
Show Author Affiliations
Ed F. A. Deprettere, Delft Univ. of Technology (Netherlands)
Marc Moonen, Katholieke Univ. Leuven (Belgium)

Published in SPIE Proceedings Vol. 2027:
Advanced Signal Processing Algorithms, Architectures, and Implementations IV
Franklin T. Luk, Editor(s)

© SPIE. Terms of Use
Back to Top