Share Email Print
cover

Proceedings Paper

CMOS processor element for a fault-tolerant SVD array
Author(s): Kishore Kota; Joseph R. Cavallaro
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper describes the VLSI implementation of a CORDIC based processor element for use in a fault-reconfigurable systolic array to compute the singular value decomposition (SVD) of a matrix. The chip implements a time redundant fault tolerance scheme, which allows processors adjacent to a faulty processor to act as computation backup during the systolic idle time. Also, processors around a fault collaborate to reroute data around the faulty processor. This form of time redundancy is attractive when tolerance to a few faults needs to be achieved with little hardware overhead.

Paper Details

Date Published: 1 November 1993
PDF: 12 pages
Proc. SPIE 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV, (1 November 1993); doi: 10.1117/12.160459
Show Author Affiliations
Kishore Kota, Rice Univ. (United States)
Joseph R. Cavallaro, Rice Univ. (United States)


Published in SPIE Proceedings Vol. 2027:
Advanced Signal Processing Algorithms, Architectures, and Implementations IV
Franklin T. Luk, Editor(s)

© SPIE. Terms of Use
Back to Top