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Proceedings Paper

Highly pipelined VLSI architecture for computation of fast Fourier transforms
Author(s): Hong-Jin Yeh
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Paper Abstract

An on-chip VLSI architecture for computation of Fourier transforms is presented. It performs the arithmetic operations in a digit-level pipeline fashion. For this purpose, the implementation of arithmetic operators is based on on-line (i.e., digit-serial and most significant digit first) arithmetic, and the transforms are performed by a parallel-pipeline version of the Cooley- Tukey fast Fourier transform (FFT) algorithm.

Paper Details

Date Published: 1 November 1993
PDF: 10 pages
Proc. SPIE 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV, (1 November 1993); doi: 10.1117/12.160427
Show Author Affiliations
Hong-Jin Yeh, Ecole Normale Superieure de Lyon (South Korea)


Published in SPIE Proceedings Vol. 2027:
Advanced Signal Processing Algorithms, Architectures, and Implementations IV
Franklin T. Luk, Editor(s)

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