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Proceedings Paper

64 x 64 thresholding photodetector array for optical pattern recognition
Author(s): Harry Langenbacher; Tien-Hsin Chao; Timothy Shaw; Jeffrey W. Yu
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Paper Abstract

A high performance 32 X 32 peak detector array is introduced. This detector consists of a 32 X 32 array of thresholding photo-transistor cells, manufactured with a standard MOSIS digital 2-micron CMOS process. A built-in thresholding function that is able to perform 1024 thresholding operations in parallel strongly distinguishes this chip from available CCD detectors. This high speed detector offers responses from one to 10 milliseconds that is much higher than the commercially available CCD detectors operating at a TV frame rate. The parallel multiple peaks thresholding detection capability makes it particularly suitable for optical correlator and optoelectronically implemented neural networks. The principle of operation, circuit design and the performance characteristics are described. Experimental demonstration of correlation peak detection is also provided. Recently, we have also designed and built an advanced version of a 64 X 64 thresholding photodetector array chip. Experimental investigation of using this chip for pattern recognition is ongoing.

Paper Details

Date Published: 25 October 1993
PDF: 9 pages
Proc. SPIE 1959, Optical Pattern Recognition IV, (25 October 1993); doi: 10.1117/12.160305
Show Author Affiliations
Harry Langenbacher, Jet Propulsion Lab. (United States)
Tien-Hsin Chao, Jet Propulsion Lab. (United States)
Timothy Shaw, Jet Propulsion Lab. (United States)
Jeffrey W. Yu, Jet Propulsion Lab. (United States)


Published in SPIE Proceedings Vol. 1959:
Optical Pattern Recognition IV
David P. Casasent, Editor(s)

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