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Proceedings Paper

Image processing system architecture using parallel arrays of digital signal processors
Author(s): Shirish P. Kshirsagar; Clifford Allan Hobson; David Andrew Hartley; David Mark Harvey
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Paper Abstract

The paper describes the requirements of a high definition, high speed image processing system. Different types of parallel architectures were considered for the system. Advantages and limitations of SIMD and MIMD architectures are briefly discussed for image processing applications. A parallel image processing system based on MIMD architecture has been developed using multiple digital signal processors which can communicate with each other through an interconnection network. Texas Instruments TMS320C40 digital signal processors have been selected because they have a powerful floating point CPU supported by fast parallel communication ports, a DMA coprocessor and two memory interfaces. A five processor system is described in the paper. The EISA bus is used as the host interface and VISION bus is used to transfer images between the processors. The system is being used for automated non-contact inspection in which electro-optic signals are processed to identify manufacturing problems.

Paper Details

Date Published: 20 October 1993
PDF: 10 pages
Proc. SPIE 2028, Applications of Digital Image Processing XVI, (20 October 1993); doi: 10.1117/12.158648
Show Author Affiliations
Shirish P. Kshirsagar, Liverpool John Moores Univ. (India)
Clifford Allan Hobson, Liverpool John Moores Univ. (United Kingdom)
David Andrew Hartley, Liverpool John Moores Univ. (United Kingdom)
David Mark Harvey, Liverpool John Moores Univ. (United Kingdom)

Published in SPIE Proceedings Vol. 2028:
Applications of Digital Image Processing XVI
Andrew G. Tescher, Editor(s)

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