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Proceedings Paper

Development of a VLSI chip set for H.261/MPEG-1 video codec
Author(s): Eishi Morimatsu; Osamu Kawai; Kiyoshi Sakai; Kiichi Matsuda; Hideki Miyasaka; Hirokazu Fukui; Yasuhiro Sakawaki; Kazuo Kaneko; Katsuhiro Eguchi
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Paper Abstract

A VLSI chip set fully compatible with both CCITT/H.261 and ISO/MPEG-1 has been developed. The chip set is composed of 3 chips, MC-LSI, COD-LSI, and DEC-LSI which realize a realtime coding of moving pictures based on the international standard coding algorithms. A realtime decoder can also be realized by single use of a DEC-LSI chip. Each chip includes 140,000 to 160,000 gates using 0.8 micrometers CMOS technology and operates at 27 MHz clock rate. The chip set performs full frame coding/decoding of CIF and SIF, and operates up to 6.3 Mb/s in the transmission bitrate. The chip set has been installed into a prototype video codec controlled by a PC(FM-TOWNS) and confirmed to work successfully.

Paper Details

Date Published: 22 October 1993
PDF: 12 pages
Proc. SPIE 2094, Visual Communications and Image Processing '93, (22 October 1993); doi: 10.1117/12.157960
Show Author Affiliations
Eishi Morimatsu, Fujitsu Labs. Ltd. (Japan)
Osamu Kawai, Fujitsu Labs. Ltd. (Japan)
Kiyoshi Sakai, Fujitsu Labs. Ltd. (Japan)
Kiichi Matsuda, Fujitsu Labs. Ltd. (Japan)
Hideki Miyasaka, Fujitsu Ltd. (Japan)
Hirokazu Fukui, Fujitsu Ltd. (Japan)
Yasuhiro Sakawaki, Fujitsu Ltd. (Japan)
Kazuo Kaneko, Fujitsu Digital Technology Ltd. (Japan)
Katsuhiro Eguchi, Fujitsu Kyushu Digital Technology Ltd. (Japan)


Published in SPIE Proceedings Vol. 2094:
Visual Communications and Image Processing '93
Barry G. Haskell; Hsueh-Ming Hang, Editor(s)

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